1. Field of the Invention
The invention relates to a solid-state imaging device including plural photodiodes in a unit pixel area, a drive method thereof and an electronic apparatus using the solid-state imaging device.
2. Description of the Related Art
Color separation in a CCD image sensor or a CMOS image sensor as a solid-state imaging device is realized by mainly using color filters. In the image sensor using color filters, a color filter of one kind is mounted with respect to one pixel, and three pixel circuits principally having color filters of red, green and blue are arranged so as to be adjacent to one another. Accordingly, light which can be received in one pixel is only one color corresponding to the color filter in a narrow sense. Therefore, in the image sensor using color filters, colors are generated by using information of light incident on adjacent pixels on which color filters of different colors are mounted.
Therefore, in the image sensor using color filters, a false color in which a color generated at an arbitrary pixel is different from a color of light which has been actually incident on the pixel occurs. Additionally, for example, in a case of a red color filter, incident lights of green and blue are absorbed by the color filter and do not reach a receiving portion by using the color filter. Therefore, more than two thirds of the incident light amount is lost. The lost of the incident light amount occurs also in green and blue color filters.
Accordingly, in order to utilize the incident light amount efficiently as well as to prevent occurrence of false colors, a method of separating colors by forming plural photodiodes in a pixel in the depth direction of a substrate has been developed.
In JP-A-2002-513145 (Patent Document 1), for example, a method of separating colors is described, in which a three-layer structure of an n-type semiconductor layer 3102, a p-type semiconductor layer 3104 and an n-type semiconductor layer 3106 is formed in a p-type Si substrate 3100, and blue, green and red lights are taken out by photoelectrically converting light in the order from a shallow-depth layer as shown in FIG. 4.
In the method, blue, green and red signals are outputted to the outside from terminals connected to respective layers on a surface of the Si substrate 3100. This utilizes the length of wavelengths and characteristics of light absorption in the depth direction. According to this, color separation in one pixel becomes possible, which can prevent occurrence of false colors. Therefore, a low-pass filter is not necessary. Furthermore, since the color filters are not used, red, green and blue colors which have different wavelengths are incident on the unit pixel. Accordingly, the loss of the light amount is reduced.
A CMOS-type solid-state imaging device is configured by arranging plural pixels in a necessary pattern, in which one pixel includes a photodiode and plural MOS transistors. The photodiode is a photoelectric conversion element which generates and accumulates signal charges in accordance with the light receiving amount, and plural MOS transistors are elements for transferring signal charges from the photodiode. In the pixels, signal charges are obtained by illuminated light and the obtained signal charges are outputted as pixel signals from respective pixels. The pixel signals outputted as the above are processed by a given signal processing circuit and outputted to the outside as video signals.
In recent years, reduction of the pixel size and improvement of a saturation charge amount (Qs) and sensitivity are addressed in order to improve characteristics of the solid-state imaging device. In JP-A-2005-223084 (Patent Document 2), a solid-state imaging device is described, which uses a charge readout transistor having a vertical gate electrode formed in the depth direction of a semiconductor substrate in order to realize the reduction of pixel size without reducing the saturation charge amount (Qs) and sensitivity.
FIG. 1A shows a schematic cross-sectional configuration of a solid-state imaging device in a related art which is described in Patent Document 2, and FIG. 1B shows a planar configuration thereof.
As shown in FIG. 1A and FIG. 1B, the solid-state imaging device in the related art includes a p-type semiconductor substrate 203, a photodiode PD included in each pixel formed in the semiconductor substrate 203 and a charge-reading transistor Tr.
The photodiode PD includes a p-type high concentration impurity region (p+region) 206 formed on the surface side of the semiconductor substrate 203, an n-type high concentration impurity region (n+region) 205 formed adjacent to the region 206 in the depth direction toward the back side and an n-type low concentration impurity region (n−region) 204. A primary pn junction “j0” included in the photodiode PD is formed by the p+region 206 and the n+region 205. As shown in FIG. 1B, the photodiode PD is formed in a photodiode region 260 in the semiconductor substrate 203, which is demarcated by a pixel isolation region 210 in each pixel.
The charge readout transistor Tr is a MOS transistor for transferring signal charges accumulated in the photodiode PD. The charge-reading transistor Tr includes a floating diffusion region 202 provided on the surface side of the semiconductor substrate 203 and a vertical gate electrode 201 formed in the semiconductor substrate 203 from the surface side in the depth direction through a gate insulating film 218. The vertical gate electrode 201 touches the floating diffusion region 202 through the gate insulating film 218 as well as is formed to reach a position deeper than the pn junction “j0” of the photodiode PD. In the vertical gate electrode 201 included in the charge readout transistor Tr, the gate insulating film 218 is formed at a groove portion formed to have the depth reaching the pn junction “j0” of the photodiode PD from the surface side of the semiconductor substrate 203. The columnar-shaped vertical gate electrode 201 is formed by filling the groove on the gate insulating film 218.
In the charge readout transistor Tr, a transfer channel is formed in the depth direction of the semiconductor substrate 203 so as to reach the floating diffusion region 202 from the pn junction “j0” included in the photodiode PD along the vertical gate electrode 201.
The solid-state imaging device is a back-illuminated solid-state imaging device illuminating light from the back side of the semiconductor substrate 203 as shown in FIG. 1B, in which the vertical gate electrode 201 included in the charge readout transistor Tr is formed at the central position of the photodiode PD.
In the solid-state imaging device having the above configuration, light incident from the back side is photoelectrically converted by the photodiode PD and signal charges are accumulated in the photodiode PD. Then, the accumulated signal charges in the photodiode PD are transferred through the transfer channel by applying positive voltage to the vertical gate electrode 201 of the charge readout transistor Tr, read out to the floating diffusion region 202 formed on the surface of the semiconductor substrate 203.
As described above, the device has the configuration in which the photodiode PD is formed in the depth direction of the semiconductor substrate 203 and signal charges accumulated in the photodiode PD are read by the vertical gate electrode 201. Accordingly, when the pixel size is reduced, the saturation charge amount (Qs) and sensitivity are not reduced. Additionally, MOS transistors and wiring layers are not formed on the light illumination side due to the back-illuminated type, therefore, an opening area can be widely secured.
On the other hand, FIG. 2A and FIG. 2B show a schematic cross-sectional configuration and a planar configuration of relevant parts of a solid-state imaging device in a related art in which the vertical gate electrode is not applied. In FIG. 2A and FIG. 2B, same symbols are given to portions corresponding to FIG. 1A and FIG. 1B and repeated explanation is omitted. As shown in FIG. 2A, when a normal planar gate electrode 301 which is not the vertical gate electrode is used, the gate electrode 301 is formed on an upper surface of the semiconductor substrate 203 at an outer peripheral portion of the photodiode region 260 in which the photodiode PD is formed through the gate insulating film 218.
The saturation charge amount (Qs) of the photodiode PD is in proportion with capacitance of the pn junction “j0” included in the photodiode PD. Since the impurity concentration is commonly high in the vicinity of the center of the photodiode PD, capacitance in a unit area is high, conversely, capacitance is low at end portions of the photodiode PD which are pixel edges. That is, in the photodiode PD shown in FIG. 1A, 1B and FIG. 2A, 2B, capacitance is high in portions surrounded by dashed lines (vicinity of the center of the photodiode region 260) and the saturation charge amount (Qs) per a unit area is also high.
According to the above, since the gate electrode 301 is formed in the outer peripheral portion of the photodiode region 260 in the example shown in FIG. 2A and FIG. 2B, the saturation charge amount (Qs) of the photodiode PD is not lost.
However, when the vertical gate is arranged at the center of the photodiode like the example shown in FIG. 1A and FIG. 1B, the vertical gate electrode 201 is buried in the portion in which capacitance is high in the photodiode PD. In this case, there is fear that the saturation charge amount (Qs) is lost in the area including the region where the vertical gate electrode 201 is formed and the periphery thereof.
When the vertical gate electrode 201 and the floating diffusion region 202 are arranged at the center of the photodiode PD included in the pixel as shown in FIG. 1A and FIG. 1B, it is difficult to share the floating diffusion region 202 among plural pixels, which makes the reduction of pixel size harder. Additionally, charges accumulated in the photodiode PD are transferred to the floating diffusion region 202 formed on the surface of the semiconductor substrate 203 through the transfer channel of the charge readout transistor Tr. Therefore, if there is a defect in the gate portion of the charge readout transistor Tr, it is anticipated that transfer failure of charges occurs or that generation of large dark current is caused. As the defect in this case, there are defects generated by processing a deep groove portion formed at the time of forming the vertical gate electrode 201 or an interface state.
The solid-state imaging device is roughly divided into an amplification-type solid-state imaging device typified by a CMOS (Complementary Metal Oxide Semiconductor) image sensor and a charge transfer-type solid-state imaging device typified by a CCD (Charge Coupled Device) image sensor. There solid-state imaging devices are widely used for a digital still camera, a digital video camera and the like. In recent years, as the solid-state imaging device mounted on mobile apparatuses such as a cellular phone with a camera and a PDA (Personal Digital Assistant), the CMOS image sensor is widely used in the light of power consumption, in which power supply voltage is low.
A CMOS solid-state imaging device is proposed (refer to Patent Document 2), in which a photoelectric conversion element (photodiode) is formed inside a p-type silicon semiconductor substrate and a vertical transfer transistor is formed to realize the reduction of pixel size without lowering the saturation charge amount (Qs) and the sensitivity. FIG. 3 shows a cross-sectional configuration of a relevant part of a pixel in the above CMOS solid-state imaging device.
A CMOS solid-state imaging device 1111 is a back-illuminated solid-state imaging device which illuminates light from the back of the substrate. In the CMOS solid-state imaging device 1111, pixel transistors included in each pixel, in this example, a transfer transistor Tr1, a reset transistor Tr2 and an amplification transistor Tr3 are formed on the front side of a semiconductor substrate 1112. A photodiode PD is formed below these pixel transistors. The photodiode PD includes an n-type semiconductor region 1113 having a high concentration impurity region (n+region) 1113A and a low concentration impurity region (n region) 1113B to be charge accumulation regions and a p-type semiconductor region (p+region) 1121 having high concentration impurity on the surface side thereof inside the semiconductor substrate 1112.
The vertical transfer transistor Tr1 is configured by including a columnar transfer gate electrode 1116 which is buried in a groove portion 1114 reaching the inside of the n-type high concentration impurity region (n+region) 1113A of the photodiode PD from the surface of the semiconductor substrate 1112 in the depth direction through a gate insulating film 1115. On the surface of the semiconductor substrate 1112, an n-type source/drain region 1117 to be a floating diffusion (FD) 40 is formed so as to touch the gate insulating film 1115. The transfer gate electrode 1116 of the vertical transfer transistor Tr1 formed at a position corresponding to the center of a unit pixel 1131, namely, the center of the photodiode PD. A p-type semiconductor region (p+region) 1121 having high concentration impurity is formed so as to surround the gate insulating film 1115 formed in the high concentration impurity region 1113A of the photodiode PD.
The reset transistor Tr2 includes a pair of n-type source/drain regions 1117, 1118 on the surface side of the semiconductor substrate 1112 and a reset gate electrode 1123 formed through the gate insulating film. The amplification transistor Tr3 includes a pair of n-type source/drain regions 1119, 1120 on the surface side of the semiconductor substrate 1112 and a reset gate electrode 1124 formed through the gate insulating film. Further, a multilevel-wiring layer in which plural layers of wirings 1126 is formed on the semiconductor substrate 1112 in which these pixel transistors (Tr1, Tr2 and Tr3) are formed through an interlayer insulating layer 1125. On the back of the semiconductor substrate 1112, color filters and on-chip micro lenses at positions corresponding to respective pixels thereabove are formed, though not shown. A numeral 1130 represents a pixel isolation region. A numeral 1131 represents a unit pixel.
Other descriptions concerning the back-illuminated solid-state imaging device are also disclosed in JP-A-2003-31785 (Patent Document 3).
As a solid-state imaging device, a CMOS solid-state imaging device is known. In the CMOS solid-state imaging device, a photodiode and plural MOS transistor forms one pixel. The solid-state imaging device having plural pixels is configured by arranging plural pixels in a necessary pattern. The photodiode is a photoelectric conversion element which generates and accumulates signal charges in accordance with the light receiving amount, and the plural MOS transistors are elements for transferring signal charges from the photodiode.
In recent years, reduction of pixel size is proceeding in the CMOS solid-state imaging device. However, since the photodiode and plural MOS transistors such as a charge readout transistor are arranged in the same plane in each pixel region in the CMOS solid-state imaging device, areas for respective elements are necessary on the plane, which tends to increase an area of one pixel. Accordingly, it is difficult to reduce the pixel size, and when the size is reduced, an area of the photodiode is also reduced, which causes problems such as the lowering of the saturation charge amount and the lowering of sensitivity.
In Patent Document 1, the configuration in which the pn junction formed in the high concentration regions of the photodiode is provided inside the semiconductor substrate is described. In this case, the channel portion of the charge readout transistor for reading signal charges is formed in the depth direction of the semiconductor substrate, and the bottom portion of the gate electrode of the reading transistor and the gate insulating film is formed at the position deeper than the depth of the pn junction. Such configuration is applied in Patent Document 2, thereby maintaining the area of the photodiode large and preventing the lowering of the saturation charge amount even when the pixel area is reduced.
However, in the solid-state imaging device of Patent Document 2, the potential which can be completely transferred with respect to one photodiode in which signal charges are accumulated in one pixel is fixed, and it is difficult to increase the saturation charge amount (Qs) more than a fixed amount. That is, it is difficult to be a configuration in which reduction of pixel size and improvement of the saturation charge amount (Qs) are realized at the same time.